Figure 3 shows a possible block diagram of the overall ADC IP using a SERDES to drive off chip. In this example, each SERDES lane uses a baud rate based on the ADC clock, so a PLL is not required. The ...

OptiCORE includes all of the features of the AlphaCORE electrical SerDes (low-power high-speed ADC, sub-sampling clock multiplier (SSCM), powerful DSP equalization including FFE and DFE, an optional ...