Switched-capacitor DAC with merging The switched-capacitor DAC architecture in fig ... The simulation refers to the worst-case corner of 1V supply, slow models and 85°C, assuming a 500mVpp input ...

This 12-bit, 500MSPS ADC supports input signals upo 100MHz and features a differential full-scale range ... The silicon-validated 12-bit Delta-Sigma ADC IP is a 1.1V low-power 12-bit 64MHz-to-340MHz ...