The USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use with host, embedded host, On-the-Go (OTG) and function ...

It conforms with the standards of UTMI+ and PIPE4.0. The USB 3.2 Gen2X1 IP contains high-speed mixed signal circuits to handle Gen2 and Gen1 traffic and is backward compatible with high-speed data ...