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Qualcomm's new chip packaging deal with UMC could upset TSMC
After all, there are multiple factors that go into the performance of a SoC, making it a success or directly ruining a good design. Chip packaging technology is one of the main keys, and TSMC also ...
SiliconANGLE23d
Report: Apple’s M5 chips will use TSMC’s N3P process and 2.5D packaging technologies
Apple will reportedly assemble the high-end M5 chips using 2.5D packaging. This is a chip design approach that places a processor’s compute modules atop a common base layer, or interposer.
Design-Reuse4y
Synopsys and TSMC Accelerate 2.5D/3DIC Designs with Chip-on-Wafer-on-Substrate and Integrated Fan-Out Certified Design Flows
Aug. 25, 2020 -- Synopsys, Inc. (Nasdaq: SNPS) today announced that Synopsys and TSMC have collaborated to deliver certified design flows for advanced packaging solutions using the Synopsys 3DIC ...